Conventional high-speed I/O data circuits to transfer large volumes of data at high speeds across short distances, such as from chip-to-chip on the same circuit board, are frequently inadequate for the task. The specifications for many industry-standard I/O interfaces were outlined nearly a decade ago, and are general purpose designs that attempt to meet a wide-range of design needs, but are not optimal for any one design. Additionally, implementations of I/O data circuits that utilize packet-based communication have a large memory requirement that may come with a significant latency penalty. Alternatively, attempts at full-custom I/O solutions are often less than optimal due to the improper application of digital design methods, induced power supply noise, and lack of signal integrity control. Chip designers are often faced with the dilemma of system implementation on a single, larger chip having a low yield and a high manufacturing cost with the benefit of faster intra-chip data communication, or system implementation with multiple chips having a higher yield and an overall lower manufacturing cost, but with slower inter-chip data communication.
A common technique for high-speed data serialization and transmission includes a 2:1 multiplexer followed by an output buffer, and uses CMOS multiplexers to generate two ½-rate NRZ data streams that are directed to a 2:1 multiplexer controlled by a ½-rate clock. The 2:1 multiplexer then sends a full-rate NRZ data stream to an output driver that is implemented either as a CML parallel-terminated driver or as a push-pull series-terminated driver. Two factors limit both maximum bandwidth and achievable power efficiency. The first factor is the design of a 2:1 multiplexer with sufficient bandwidth to avoid inter-symbol interference (ISI) at the output, because any ISI-induced data-dependent jitter is further amplified by the output driver and channel due to finite bandwidth. This design limitation can be accounted for through appropriate sizing of the 2:1 multiplexer, but this in turn can lead to excessive power consumption. The second factor is that setup and hold time requirements for the 2:1 multiplexer is increasingly difficult to achieve reliably at very high data rates.